1. Field of the Invention
The invention relates to an integrated circuit constituted of semiconductor devices for operation and storage which are widely utilized in electronic devices such as a computer and communication devices. More particularly, the invention relates to a high electron mobility transistor (HEMT) using two-dimensional electron gas or two-dimensional hole gas as carriers.
2. Description of the Related Art
There are many methods of enhancing mobility of carriers in a semiconductor device. As one of such methods, there has been suggested HEMT in Japanese Journal of Applied Physics, Vol. 225, No. 19, 1980. The suggested HEMT is made of compound semiconductor such as GaAs, and utilizes a quantum well or potential well as a channel of a transistor. Such a quantum or potential well is formed by band off-set caused by joining two semiconductors having different electron affinity to each other. With regard to silicon which is mainly used to make memory and logic transistors thereof, there has been suggested HEMT made of Si/SiGe family utilizing a difference in electron affinity therebetween (Applied Physics Letters, Vol. 45, No. 11, 1984, pp. 1231-1233).
However, it is quite difficult to form qualified heterojunction because of a difference in lattice constant between Ge and Si. Thus, Japanese Unexamined Patent Publication No. 62-86867 has suggested HEMT made of silicon family, including a semiconductor layer 40 made of crystal silicon, an amorphous SiC layer 41 having smaller electron affinity than that of the crystal silicon layer 40, and a gate electrode 42 formed on the amorphous SiC layer 41. The suggested HEMT utilizes an interface between the amorphous SiC layer 41 and the crystal silicon layer 40 to thereby accomplish higher mobility in a transistor.
However, the above mentioned conventional HEMT has problems as follows.
The first problem is that even if impurities were doped into the amorphous SiC layer as a carrier supply, it would be impossible to have a desired carrier concentration. This is because that since SiC is in amorphous condition and hence there are a lot of dangling bonds in the amorphous SiC layer 41, electrons or holes as carriers are trapped with such dangling bonds.
The second problem is that it is quite difficult to have a qualified interface between a crystal silicon layer and an amorphous SiC layer. The reason is as follows. When an amorphous SiC layer is made to grow by means of chemical vapor deposition (CVD) or molecular beam epitaxy (MBE), the amorphous SiC layer is influenced by an underlying silicon layer at an initial stage in growth, and thus grains tend to be formed at an interface between a crystal silicon layer and an amorphous SiC layer. Thus, the interface that is intended to be used as a channel becomes irregular, which does not ensure normal transistor operation.
The third problem is that there would be caused a risk of an increase in fabrication costs. The reason is that it would be necessary to prepare an apparatus for carrying out CVD used only for growth of SiC.